Scrambler and scrambling method

ABSTRACT

A scrambler and scrambling method. The scrambler has a random data generator which generates random data having a random data generation cycle based on a result obtained by multiplying at least a size of a first data frame by a result obtained by dividing a data amount of two tracks in an outermost circumference of an optical disc by a size of a second data frame. The scrambler is advantageous in generating a stable servo signal and suppressing a DC component in modulation in a high density disc system using the optical disc.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This is application is a continuation of prior U.S. patent application Ser. No. 09/620,462 filed Jul. 20, 2000. This application claims the benefit of Korean Application No. 99-29280, filed Jul. 20,1999, in the Korean Patent Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to data scrambling, and more particularly, to a scrambler and a scrambling method appropriate for a high density disc system.

[0004] 2. Description of the Related Art

[0005] In general, the goal of data scrambling is to protect data from users who do not have key. For telecommunications, data scrambling is a widely used randomizing method for security communications purposes.

[0006] An optical disc system using an optical disc, such as a compact disc-read only memory (CD-ROM) or a digital versatile disc (DVD), adopts a random data generator which randomizes certain data input into a scrambler.

[0007] The first reason for scrambling input data in an optical disc system is to smoothly perform tracking control using differential phase detection (DPD). If identical data are input and the same modulated codes of the identical data are recorded in neighboring tracks on a disc, DPD signals are not detected during reproduction and tracking control in a servo unit becomes difficult. For example, in an unscrambled CD-audio disc, DPD control becomes difficult in a section between songs (a section in which data are all “00h”).

[0008] The second reason for scrambling is to help reduce a burden to control suppression of a direct current (DC) component in a modulator. When identical data are continuously input, digital sum value (DSV) control may be impossible for some values. In order to prevent such worst cases, randomizing is needed. Here, the DSV is a parameter for predicting the DC direction, and it is preferable that a modulated code word has a characteristic of converging into a DC value.

[0009] The third reason for scrambling is to protect certain data. In the case of a CD-ROM, in order to protect a synchronization pattern (00h, FFh, FFh, . . . , FFh, 00h) in data, scrambling is performed on all data except synchronization data.

[0010] Referring to FIG. 1, the periodicity of a scrambler for a general DVD system will now be explained. Since the length of a channel bit is 0.133 m, the physical length of a sector is 5.146 mm (=0.133 m×1488×26), the radius of the innermost circumference of a disc 5 is 24 mm (as shown in FIG. 1), the track length of the innermost circumference is 150.8 mm (=2πr) and the track capacity of the innermost circumference is 29.3 sectors (=150.8 mm/5.146 mm). In addition, since the radius of the outermost circumference is 58 mm as shown in FIG. 1, the track length of the outermost circumference is 364.42 mm (=2πr) and the track capacity of the outermost circumference is 70.82 sectors (364.42 mm/5.146 mm).

[0011] For DPD control, the cycle of random data generation of a scrambler must be equal to or greater than 141.64 sectors (=70.82 sector×2) in the outermost circumference. Identical data repeating within 29.3 sectors in the innermost circumference do not cause any problem in DPD control.

[0012]FIG. 2 illustrates a circuit diagram of a scrambler in a DVD system, in which an exclusive-or (XOR) gate 10 and 15 registers r₀ through r₁₄ for supplying random data are referred to as a random data generator. The random data generator and XOR gates 11 through 18 are referred to as a scrambler.

[0013] The 15 registers r₀ through r₁₄ in FIG. 2 perform left shifting in synchronization with a clock signal for scrambling, which is not shown in FIG. 2. During the scrambling, an XOR value obtained from XOR gate 10 by XORing the output of the most significant register r₁₄ and the output of the 11^(th) lowest register r₁₀, becomes an input value to the least significant register r₀.

[0014] The cycle of random data generation of the random data generator in FIG. 2 is 32K (kilobytes), and matches the 32K-size of 1 error correction code (ECC) block of a DVD. That is, random data without a periodicity are generated in one ECC block, and after left-shifting the 15 registers r₀ through r₁₄ 8 times, the result D₀₁ through D₀₇ of XORing each of the 8 outputs of the lower registers r₀ through r₇ and 1-byte input data D₀ through D₇ in XOR gates 11 through 18 is obtained as the result of scrambling. Here, the data clock speed of XOR gates 11 through 18 is an eighth of the scramble clock speed of the registers r₀ through r₁₄, which is not shown in FIG. 2.

[0015] In the meantime, since scrambling is performed after left-shifting the 15 registers r₀ through r₁₄, 8 times, registers r₀ through r₁₄ are initialized by preset values, referring to the upper significant 4 bits (ID 7:4) in the last one byte in a 4-byte identification code (ID) allocated to each sector. At this time, selection of initial values needs to be handled carefully. That is, even if identical data are input, random data must be generated using the identical initial value in a sector, and random data in this sector are repeated by the identical initial value for one ECC block (16 sectors).

[0016] As shown in FIG. 3, the first initial value of registers r₀ through r₁₄ “0001 h” and the result of left-shifting “0001h” 7 times are 0002h, 0004h, 0008h, 0010h, 0020h, 0040h, 0080h; the result of left-shifting 7 times “5500h”, the value of registers r₀ through r₁₄ after 16K (=2K×8) capacity required for the return of the values 0001h, 0002h, 0004h, 0008h, 0010h, 0020h, 0040h, 0080h, are 2A00h, 5400h, 2800h, 5000h, 2001h, 4002h, 0005h; and 0001h, 0002h, 0004h, 0008h, 0010h, 0020h, 0040h, 0080h, 5500h, 2A00h, 5400h, 2800h, 5000h, 2001h, 4002h, 0005h, which are used for initial values of r₀ through r₁₄.

[0017] The scrambler of FIG. 2 uses all of the 32K of random data generated by the random data generator, and sector data in one ECC block are repeated. However, the scrambler of FIG. 2 does not have the DPD control problem mentioned in FIG. 1. In addition, since random data are generated for one sector during modulation, there is no DSV control. Using the initial values of registers shown in FIG. 3, identical data are not generated contiguously between ECC blocks during 256 sectors (=1 ECC block (16 sectors)×16 times initialization). Therefore, since identical code data do not occur in contiguous tracks in the outermost circumference of a disc, there is no problem in DPD control.

[0018] However, the previous random data generator and the scrambler using the random data generator cannot respond properly when generation of random data having a cycle greater than 32K and corresponding scrambling are required.

SUMMARY OF THE INVENTION

[0019] To solve the above problems, it is an object of the present invention to provide a scrambler appropriate for high density optical disc systems, by controlling the cycle of random data generation.

[0020] It is another object to provide a scrambler which is advantageous in generating stable servo signals and suppressing a direct current (DC) component in modulation.

[0021] It is still another object to provide a method of scrambling which is appropriate for high density optical disc systems, by controlling the cycle of random data generation.

[0022] It is yet still another object to provide a method of scrambling which is advantageous in generating stable servo signals and suppressing a direct current (DC) component.

[0023] Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

[0024] To accomplish the above and other objects of the present invention, there is provided a data scrambler for a high density optical recording/reproducing apparatus, the data scrambler having a random data generator which generates random data having a random data generation cycle based on a result obtained by multiplying at least a size of a first data frame by a result obtained by dividing a data amount of two tracks in an outermost circumference by a size of a second data frame

[0025] There is also provided a data scrambling method using a random data generator for a high density optical recording/reproducing apparatus, the data scrambling method comprising generating random data having a random data generation cycle based on a result by multiplying at least the size of a first data frame by a result, which is obtained by dividing a data amount of two tracks in an outermost circumference of a disc by a size of a second data frame.

[0026] Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and other objects and advantages of the invention will become apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:

[0028]FIG. 1 is a general diagram showing an inner circumference and an outer circumference of a disc;

[0029]FIG. 2 illustrates a circuit diagram of a scrambler in a general digital versatile disc (DVD) system;

[0030]FIG. 3 is a table showing initial values used in registers shown in FIG. 2;

[0031]FIG. 4 illustrates a circuit diagram of an embodiment of a scrambler for a high density disc system according to the present invention;

[0032]FIG. 5 is a table showing initial values of registers used in the 8-bit shift-scrambler shown in FIG. 4;

[0033]FIG. 6 illustrates a generalized circuit diagram of a scrambler for high density disc system to explain the present invention;

[0034]FIG. 7 is a table showing branch values when a random data cycle is 64K and the number of effective branches is 4 in the random data generator shown in FIG. 6;

[0035]FIG. 8 is a table showing initial values of registers used in a 1-bit shift-scrambler for a high density disc system according to the present invention;

[0036]FIG. 9 is a circuit diagram of another embodiment of a scrambler for a high density disc system according to the present invention; and

[0037]FIG. 10 is a table showing the control values for changing the structure of a scrambler, shown in FIG. 9, in the units of 4K cycle.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Reference will now made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiments, and many variations are possible within the spirit and scope of the present invention. The embodiments of the present invention are provided in order to more completely explain the present invention to anyone skilled in the art. Like reference numerals refer to like elements throughout.

[0040] First, the periodicity of the scrambler in a high density DVD system will be explained.

[0041] When it is assumed that compared to a general DVD, an HD-DVD has the same innermost circumference and outermost circumference, but has a line density which is twice as high, the track length of the innermost circumference is 150.8 mm (=2πr×24 mm), the track capacity of the innermost circumference is about 120 KB (=60×2 KB), the track length of the outermost circumference is 364.42 mm (=2πT×58 mm), and the track capacity of the outermost circumference is about 284 KB (=142×2 KB).

[0042] When it is assumed that the line density of an HD-DVD is twice as high as that of a DVD, the cycle of random data generation of a scrambler in the outermost circumference must be equal to or greater than 564(=284K×2) in order to control DPD, and even when identical data are repeated within 120K, no DPD control problem occurs in the innermost circumference.

[0043] However, in an HD-DVD, the structure of a scrambler changes depending on whether or not the size of a sector will be 2 KB, or 4 KB, or whether or not the size of an ECC block will be 32 sectors, or 16 sectors, which will now be explained in detail.

[0044] First, for the structure of a scrambler for an HD-DVD system having 2 KB for a sector and 32 sectors for an ECC block, the scrambler for a general DVD system shown in FIG. 2 can be used.

[0045] That is, since 120K, the track capacity of the innermost circumference, is greater than one ECC block (64 KB) and smaller than two ECC blocks (128 KB), the initial value of each sector in an ECC block can be set to an identical value. In order to prevent repeating of the same data of two tracks in the outermost circumference, a periodicity equal to or more than 564 K is needed. With only 16 initial values, the cycle of random data generation becomes 1024 K (=1 ECC block (64 KB)×16), which is greater than 564 KB and causes no problem. Therefore, the same structure as that of the scrambler for a general DVD system shown in FIG. 2 can be used for an HD-DVD system.

[0046] Next, for the structure of a scrambler having 4 KB for a sector and 16 sectors for an ECC block, the scrambler for a general DVD system cannot be used, and the structure of a scrambler must be changed.

[0047] Since 120 K, the track capacity of the innermost circumference, is greater than one ECC block (64 KB) and smaller than two ECC blocks (128 KB), the initial value of each sector in an ECC block can be set to an identical value.

[0048] Also, in the outermost circumference, in order to obtain a periodicity equal to or more than 564 K, the cycle of random data generation becomes 1024 K (=1 ECC block (64 KB)×16) with only 16 initial values, which causes no problem. However, since the cycle of random data generation of the random data generator of the scrambler must be equal to or greater than 64 KB (=1 sector (4 KB)×16), the structure of the scrambler in a general DVD as shown in FIG. 2 cannot be used.

[0049] Therefore, the present invention proposes three types of scramblers, having a cycle of random data generation equal to or greater than 64 K.

[0050] The first structure of a scrambler according to the present invention is shown in FIG. 4, and the structure of the scrambler for an HD-DVD system has some similarities to that of a scrambler for a general DVD system shown in FIG. 2.

[0051] That is, 16-bit random data is generated in 16 registers r₀ through r₁₅, and the result D₀₁ through D₀₇ of scrambling through XOR gates 111 through 118 1-byte of input data D₀ through D₇ and outputs of the lower 8 registers r₀ through r₇ is provided. The XOR gate 103 XORs the output of the most significant register r₁₅ and the output of the register r₁₃, the XOR gate 102 XORs the output of the XOR gate 103 and the output of the register r₁₂, and the XOR gate 101 XORs the output of the XOR gate 102 and the output of the register r₁₀ and feeds back its output to the least significant register r₀.

[0052]FIG. 5 is a table showing initial values of registers used in the 8-bit shift-scrambler for an HD-DVD system shown in FIG. 4. Scrambling is performed in units of 1 byte between the bits of the lower 8 registers r₀ through r₇ and 1 byte of input data D₀ through D₇, after 8-bit left-shifting the output of the registers r₀ through r₁₅. Therefore, for the initial values of the registers, 0001h and the values obtained by left-shifting 0001h (0002h, 0004h, 0008h, 0010h, 0020h, 0040h, 0080h), and 7E80h, which is the result of registers r₀ through r₁₅ after 32 K (4 K×8 times) that is required for returning these values, and the values obtained by left-shifting 7E80h (FF01h, FE02h, FC04h, F808h, F011h, E023h, C046h) are used.

[0053] Here, diverse examples of scramblers adopting a random data generator having a 64 K random data generation cycle, as shown in FIG. 4, are disclosed in the Korean Patent Application No. 99-27886, filed by the present applicant on 10 Jul. 1999, under the title of “Random Data Generator and a Scrambler Using the Random Data Generator”.

[0054] Referring to FIGS. 6 and 7, a generalized structure of a scrambler shown in FIG. 4 and mentioned in the above application will now be described in order to help explain the present invention.

[0055] For example, a branch table 200, shown in FIG. 7, of a scrambler shown in FIG. 6 stores the branch values B_(o0) through B_(o15) for all possible cases when the number of effective branches of the XOR gates G₀ through G₁₅ of a random data generator is 4. The scrambler in FIG. 4 is implemented in a simple structure in a case where the value of a branch is “B400h”.

[0056] In FIG. 6, when any one value stored in the branch table 200 is selected, the multiplexors m₀ through m₁₅ receive the 16 output bits B_(o0) through B_(o15), respectively, according to the selected branch value, as a selection signal. When values of the outputs B_(o0) through B_(o15) of the branch table 200 are “1”, corresponding multiplexors of m₀ through m₁₅ supply “0”, which is input to the first input end (A), to one end of corresponding XOR gates G₀ through G₁₅, as an output signal Mo₀ through Mo₁₅. Corresponding XOR gates G₀ through G₁₅ output values of S₀ through S₁₅ of each corresponding register r₀ through r₁₅ , which are input to the other end of each XOR gate G₀ through G₁₅, without change, and the accumulated output value of XOR gate G₀ is finally fed back and input to the least significant register r₀.

[0057] In addition, when values of the outputs B_(o0) through B_(o15) of the branch table 200 are “0”, corresponding multiplexors of m₀ through m₁₅ supply the outputs So through S₁₅ of each register r₀ through r₁₅, which is input to the second input end (B), as its own output signal Mo₀ through Mo₁₅. Then, corresponding XOR gates of G₀ through G₁₅ XOR S₀ through S₁₅, which is the output of each multiplexor m₀ through m₁₅, and S₀ through S₁₅, which is the output of each register r₀ through r₁₅. At this time, since the outputs of corresponding XOR gates G₀ through G₁₅ finally become “0”, no feedback value is input to the least significant register r₀.

[0058] By doing so, 64 K random data from each register r₀ through r₁₅ are generated during one ECC block, and the result D₀₁ through D₀₇ of scrambling by XORing 8 bits of input data D₀ through D₇ and the outputs of the lower 8 registers r₀ through r₇, respectively, in XOR gates 201 through 208, respectively, is provided.

[0059] Here, if the number of registers is 16, the cycle of random data becomes 2¹⁶ (=approximately 64 K), and if the number of registers is n, the cycle of random data can be expanded to 2^(n).

[0060] The second structure of a scrambler according to the present invention has the same structure as the scrambler shown in FIG. 4 or FIG. 6. As shown in FIG. 8, however, since its scrambling is performed in units of the lower 8 bits of registers r₀ through r₇ and 1 byte input data after left-shifting every one bit, the initial values of registers r₀ through r₁₅, which are determined by the upper 4 bits (ID(7:4)) of the last byte in a 4-byte identification code (ID), which is allocated to each sector, are different from the initial values shown in FIG. 5. The initial values in FIG. 8 are the initial values used in the scrambler of FIG. 4.

[0061] That is, the first preset value 0001h and the values (3DADh, D4E7h, FDCAh, EBCCh, 292Eh, 50Fh, 50F0h, BFCAh, 7F80h, D36Eh, BB39h, 5DFFh, A809h, 6647h, 8044h, 0304h) of registers r₀ through r₁₅, which are obtained after each 4,096 times left-shifting are used as the initial values, which is different from the initial values of FIG. 5.

[0062] The second structure of a scrambler according to the present invention has merit in that a serial structure as shown in FIG. 4 or FIG. 6 need not be changed into a parallel structure in response to a need for high speed.

[0063] The third structure of a scrambler according to the present invention is shown in FIG. 9. While the structure of the scramblers in FIG. 4 and FIG. 6 have registers r₀ through r₁₅ for generating random data having a 64 K cycle and perform scrambling with changing initial values in each sector, the scrambler in FIG. 9 has 16 kinds of decoding values, each for generating random data having a 4 K cycle, and changes the effective structure of a random data generator according to the upper 4 bits (ID(7:4)) of the last byte in a 4-byte identification code (ID) which is allocated to each sector.

[0064] The scrambler of FIG. 9 has a random data generator having a 4×16 decoder 300, 12 multiplexors m₀ through m₁₁, 12 XOR gates G₀ through G₁₁, and 12 registers r₀ through r₁₁, and the scrambler further has XOR gates 301 through 308 for outputting the result D₀₁ through D₀₇ of scrambling by XORing 8-bits of input data D₀ through D₇ and the outputs of the lower 8 registers r₀ through r₇, respectively. Here, the 12 multiplexors can be collectively referred to as a selection output circuit, which selectively outputs “0” or the output of each register according to the 12-bit output of the 4×16 decoder 300, and the 12 XOR gates G₀ through G₁₁ be referred to as a logic circuit, which supplies the 12-bit result of XORing to the least significant register r₀.

[0065] When one of the control values (829h, 834h, 84Ch, 868h, 883h, 891h, 8B0h, 8C2h, 906h, 960h, 990h, A03h, A18h, B04h, C48h, CA0h), as shown in FIG. 10, for controlling changes in the structure of the 16 scrambler configurations (in the scrambler, since the logical existence of each of the multiplexors M₀ through M₁₁, can be controlled by the bit values B₀ through B₁₁ input thereinto from the 4×16 decoder 300, although the scrambler maintains the same physical structure, it can be configured in 16 different ways) according to the upper 4 bits (ID(7:4)) of the last 1 byte in a 4-byte identification code allocated to each sector is input every one ECC block, the 4×16 decoder 300 in FIG. 9 supplies a 12-bit output corresponding to the control value, and among the 12-bit output Bo₀ through Bo₁₁, only those branches which have “1” are effective. The 4×16 decoder can output 16 kinds of decoding values according to its 4-bit inputs. Here, the initial values of registers r₀ through r₁₁ are set in units of one ECC block, and, for example, the initial values are set to “001h”.

[0066] The multiplexors m₀ through m₁₁ receive the 12 output bits B_(o0) through B_(o11) as a selection signal, and when values of the outputs Bo₀ through B₀₁₁ of the 4×16 decoder 300 are “1”, corresponding multiplexors m₀ through m₁₁, supply “0”, which is input to the first input end (A), to one end of corresponding XOR gates of G₀ through G₁₁, as an output signal Mo₀ through Mo₁₁. Corresponding XOR gates of G₀ through G₁₁ output values of S₀ through S₁₁ of each corresponding register r₀ through r₁₁, which are input to the other end of each XOR gate G₀ through G₁₅, without change, and the accumulated output value of XOR gate G₀ is fed back and input to the least significant register r₀.

[0067] In addition, when values of the outputs B_(o0) through B_(o11) of the 4×16 decoder 300 are “0”, corresponding multiplexors of m₀ through m₁₁ supply the outputs S₀ through S₁₁ of each corresponding register r₀ through r₁₁, which is input to the second input end of the second input end (B), as its own output signal Mo₀ through Mo₁₁. Then, corresponding XOR gates of G₀ through G₁₁ XOR S₀ through S₁₁, which are the output of each multiplexor m₀ through m₁₁, and S₀ through S₁₁, which are the output of the corresponding registers r₀ through r₁₁. At this time, since the output of the corresponding XOR gates G₀ through G₁₁ finally become “0”, no feedback value is input to the least significant register r₀.

[0068] By doing so, 4K of random data from each register r₀ through r₁₁ are generated in units of a sector, and the result D₀₁ through D₀₇ of scrambling by XORing 1 byte of input data D₀ through D₇ and each output of the lower 8 registers r₀ through r₇ in XOR gates 301 through 308 is provided.

[0069] Thus, the structure of a scrambler can be changed depending on the capacity of the innermost circumference track, the capacity of the outermost circumference track, the size of a sector and the size of an ECC block. That is, a system using an HD-DVD, in which the sector size is 2KB and the ECC block size is 32 sectors, can use the scrambler which is used in a general DVD system, without change. Meanwhile, a system using an HD-DVD, in which the sector size is 4 KB and the ECC block size is 16 sectors, can use one of the three types below.

[0070] N) scrambled data is output when a random generator performs an 8-bit shift: FIG. 4 (FIG. 6)+FIG. 5;

[0071] Ii) scrambled data is output when a random data generator performs a 1-bit shift: FIG. 4 (FIG. 6)+FIG. 8; or

[0072] Iii) a random data generator whose structure can be changed according to the decoding values: FIG. 9+FIG. 10.

[0073] In the meantime, the conditions for the random data generation cycle of a random data generator used in a scrambler for an optical disc system will now be explained.

[0074] When it is assumed that a first data frame (Data Frame 1) is a sector, a second data frame (Data Frame 2) is an ECC block, the data amount in the first data frame is b, the data amount in the second data frame is B, the data amount in the innermost circumference track is A, and the data amount of two tracks in the outermost circumference is C, the following condition 1, condition 2, and condition 3 must be met, and the random data generation cycle of the random data generator in a scrambler of an optical system must be equal to or greater than B. The same values from the random data generator or the same decoding values can be used while the random data generator does not exceed α×/B.

Data Frame 2=n×Data Frame 1, n is an integer  Condition 1

|A/B|=α, |A/B| represents the integer part of A/B.  Condition 2

b×C/B=B.  Condition 3

EXAMPLE 1

[0075] A General DVD

[0076] When Data Frame 1=2K (b), Data Frame 2=32K (B), and the data amount of two tracks in the outermost circumference=284 K (C), a random data generation cycle must be equal to or greater than 17.75 K (=2 K×284/32 K), and the random data generation cycle of a scrambler in an actual DVD is 32K. |A/B|=int |60K/32K|=α=1, α×B=32K. Therefore, it is possible to use an initial value or a decoding value which the random data generator cycle does not exceed 32K.

EXAMPLE 2

[0077] The first case of an HD-DVD having a line density in a tangential direction twice as high as that of a DVD

[0078] When Data Frame 1=4 K (b), Data Frame 2=64 K (B), and the data amount of two tracks in the outermost circumference=568 K (C), a random data generation cycle must be equal to or greater than 35.5 K (=4 K×568/64 K). Since α=int |120K/64K|=1, it is possible to use an initial value or a decoding value while the random data generation cycle does not exceed 64K.

EXAMPLE 3

[0079] The second case of an HD-DVD having a line density in a tangential direction twice as high as that of a DVD

[0080] When Data Frame 1=8 K (b), Data Frame 2=64 K (B), and the data amount of two tracks in the outermost circumference=568 K (C), a random data generation cycle must be equal to or greater than 71 K (=8 K×568/64 K). Since α=int |120K/64K|=1, it is possible to use an initial value or a decoding value while the random data generation cycle does not exceed 64K.

EXAMPLE 4

[0081] The third case of an HD-DVD having a line density in a tangential direction twice as high as that of a DVD

[0082] When Data Frame 1=2 K (b), Data Frame 2=64 K (B), and the data amount of two tracks in the outermost circumference=568 K (C), a random data generation cycle must be equal to or greater than 17.75 K (=4 K×568/64 K), and the scrambler of a general DVD system can be used. Since α=int |120K/64K|=1, it is possible to use an initial value or a decoding value while the random data generation cycle does not exceed 64K.

[0083] The present invention can be used in equipment using data scrambling, and particularly, can be efficiently used in a high density disc system.

[0084] The scrambling method of the scrambler according to the present invention is advantageous in generating a stable servo signal and suppressing the DC component in modulation in high density optical recording/reproducing apparatuses. In addition, since the scrambler can generate random data having a long cycle of equal to or greater than 64 K, it can be applied to an HD-DVD system.

[0085] Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents. 

What is claimed is:
 1. A recording/reproducing apparatus comprising; a data scrambler having a random data generator for generating random data in a cycle of 32 KB in order to scramble data having structure of 2 KB for a sector or a data frame and 64 KB for an ECC block.
 2. The apparatus of claim 1, wherein the random data generator comprises: a 15-bit serial register r₀ through r₁₄ for generating the random data by shifting left synchronized with a clock input for scrambling; and an exclusive OR gate for outputting an exclusive OR value exclusive-ORing output from a higher-most register r₁₄ and output from a lower register r₁₀ to a lower-most register r₀, wherein the scrambler includes an exclusive OR logic circuit which supplies a result of exclusive-ORing 1-byte input data D₀ through D₇ and each of the 8 outputs of lower registers r₀ through r₇ after left-shifting the 15-bit register r₀ through r₁₄ 8 times. 